set_property SRC_FILE_INFO {cfile:D:/code/verilog/FPGA_Project/ceres/ceres.srcs/constrs_1/new/ceres_noOutput.xdc rfile:../../../ceres.srcs/constrs_1/new/ceres_noOutput.xdc id:1} [current_design]
set_property src_info {type:XDC file:1 line:1 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN U18 [get_ports clk_i]
set_property src_info {type:XDC file:1 line:4 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN N15 [get_ports rst_i]
